1. Field of the Invention
The present invention relates to a buffer memory controller and, more particularly, to a controller for sequentially assigning input sample data in a memory, and separating and extracting the sample data stored.
2. Description of the Related Art
Generally speaking, two memories for respectively buffering and processing are required in order to implement a digital audio decoder. FIG. 1 shows the construction of a memory to which sample data are assigned in a bit stream input. For instance, it is observed that five samples of different numbers of bit of the following bit stream are stored in an 8-bit word memory.
TABLE 1 ______________________________________ 2 bit 6 bit 3 bit 8 bit 1 bit ______________________________________
The size of the memory can be determined by the sample frequency, bit rate, and the number of samples per frame. Herein, the size of the memory is assumed to be 8 bit.times.1024 words. The number of sample bits corresponds to 2 to 16. Namely, the maximum number of sample bits is 16.
Conventionally, when the buffer memory receives the bit stream exemplified in the above Table 1, it stores the sampled data in a one-word format. In other words, each sampled data is assigned to one word of the memory regardless of the number of bits. Accordingly, memory area is wasted when the sampled data is less than 8 bits.